{"id":267,"date":"2020-08-18T19:23:47","date_gmt":"2020-08-18T20:23:47","guid":{"rendered":"http:\/\/www.linux-tutorial.info\/?page_id=77"},"modified":"2020-08-22T19:26:01","modified_gmt":"2020-08-22T20:26:01","slug":"this-is-the-page-title-toplevel-102","status":"publish","type":"page","link":"http:\/\/www.linux-tutorial.info\/?page_id=267","title":{"rendered":"Industry Standard Architecture ISA"},"content":{"rendered":"\nIndustry Standard Architecture ISA<\/title>\n<p>\nAs I mentioned before,\nmost people are generally aware of the relationship between\n<glossary>CPU<\/glossary> performance and system performance. However, every\nsystem is only as strong as its weakest component. Therefore, the expansion\n<glossary>bus<\/glossary> also sets limits on the system performance.\n<\/p>\n<p>\nThere were several drawbacks with the original expansion\n<glossary>bus<\/glossary> in the original IBM PC. First, it was limited to only 8\ndata lines, which meant that only 8 bits could be transferred at a time.\nSecond, the <glossary>expansion bus<\/glossary> was, in a way, directly connected\nto the <glossary>CPU<\/glossary>. Therefore, it operated at the same speed as\nthe CPU, which meant that to improve performance with the CPU, the expansion bus\nhad to be altered as well. The result would have been that existing expansion\ncards would be obsolete.\n<\/p>\n<p>\nIn the early days of PC computing, IBM was not\nknown to want to cut its own throat. It has already developed quite a following\nwith the IBM PC among users and developers. If it decided to change the design\nof the expansion <glossary>bus<\/glossary>, developers would have to re-invent\nthe wheel and users would have to buy all new equipment. There was the risk that\nusers and developers would switch to another platform instead of sticking with\nIBM.\n<\/p>\n<p>\nRather than risk that, IBM decided that backward compatibility was\na paramount issue. One key change was severing the direct connection between\nthe expansion <glossary>bus<\/glossary> and <glossary>CPU<\/glossary>. As a\nresult, expansion boards could operate at a different speed than the CPU,\nenabling users to keep existing hardware and enabling manufacturers to keep\nproducing their expansion cards. As a result, the IBM standard became the\nindustry standard, and the bus architecture became known as the Industry\nStandard Architecture, or <glossary>ISA<\/glossary>.\n<\/p>\n<p>\nIn addition to this\nchange, IBM added more <glossary>address<\/glossary> and data lines. They doubled\nthe data lines to 16 and increased the address lines to 24. This meant that the\nsystem could address up to 16 megabytes of memory, the maximum that the 80286\n<glossary>CPU<\/glossary> (Intel’s newest central processor at the time) could\nhandle.\n<\/p>\n<p>\nWhen the 80386 came out, the connection between the\n<glossary>CPU<\/glossary> and <glossary>bus<\/glossary> clocks were severed\ncompletely because no expansion board could operate at the 16MHz or more that\nthe 80386 could. The bus speed does not need to be an exact fraction of the CPU\nspeed, but an attempt has been made to keep it there because by keeping the bus\nand CPU synchronized, it is easier to transfer data. The CPU will only accept\ndata when it coincides with its own clock. If an attempt is made to speed the\nbus a little, the data must wait until the right moment in the CPUs clock cycle\nto pass the data. Therefore, nothing has been gained by making it faster.\n<\/p>\n<p>\nOne method used to speed up the transfer of data is\n<glossary>Direct Memory Access<\/glossary>, or\n<glossary>DMA<\/glossary>. Although DMA existed in the IBM\nXT, the ISA-Bus provided some extra lines. DMA enables the system to move data\nfrom place to place without the intervention of the <glossary>CPU<\/glossary>.\nIn that way, data can be transferred from, lets say, the hard disk to memory\nwhile the CPU is working on something else. Keep in mind that to make the\ntransfer, the DMA controller must have complete control of both the data and the\n<glossary>address<\/glossary> lines, so the CPU itself <em>cannot<\/em> access\nmemory at this time. What DMA access looks like graphically we see in Figure\n0-1.\n<\/p>\n<p>\n<img decoding=\"async\" src=\"dma.png\" width=333 height=398 border=0 usemap=\"#dma_map\">\n<map name=\"dma_map\">\n<area shape=\"RECT\" coords=\"0,148,190,248\" href=\"popup#Direct Memory Access#The CPU sends commands to the DMA controller.\">\n<area shape=\"RECT\" coords=\"194,146,326,248\" href=\"popup#Direct Memory Access#The DMA controller acts as intermediary between RAM and devices like hard disks, or CD-ROMs.\">\n<area shape=\"RECT\" coords=\"198,2,329,104\" href=\"popup#Direct Memory Access#Transfer speeds to and from RAM can be increased if the CPU does not have to deal with it directly.\">\n<area shape=\"RECT\" coords=\"192,290,331,395\" href=\"popup#Direct Memory Access#DMA capable devices make request of the DMA controll, which writes to or reads from RAM.\">\n<\/map>\n<p>\n<icaption>Image –\nDirect Memory Access (<b>interactive<\/b>)<\/icaption>\n<\/p>\n<p>\nLets step back here\na minute. It is somewhat incorrect to say that a <glossary>DMA<\/glossary>\ntransfer occurs without intervention from the <glossary>CPU<\/glossary>, as it is\nthe CPU that must initiate the transfer. Once the transfer is started, however,\nthe CPU is free to continue with other activities. DMA controllers on ISA-Bus\nmachines use “pass-through” or “fly-by” transfers. That is, the data is not\nlatched or held internally but rather is simply passed through the controller.\nIf it were latched, two cycles would be needed: one to latch into the DMA\ncontroller and another to pass it to the device or memory (depending on which\nway it was headed).\n<\/p>\n<p>\nDevices tell the <glossary>DMA<\/glossary> controller\nthat they wish to make DMA transfers through one of three “DMA Request” lines,\nnumbered 13. Each of these lines is given a priority based on its number, 1\nbeing the highest. The ISA-Bus includes two sets of DMA controllers: four 8-bit\nchannels and four 16-bit channels. The channels are labeled 07, 0 having the\nhighest priority.\n<\/p>\n<p>\nEach device on the system capable of doing\n<glossary>DMA<\/glossary> transfers is given its own DMA channel. The channel is\nset on the expansion board usually by means of jumpers. The pins to which these\njumpers are connected are usually labeled DRQ, for DMA Request.\n<\/p>\n<p>\nThe two\n<glossary>DMA<\/glossary> controllers (both Intel 8237), each with four DMA\nchannels, are cascaded together. The master DMA controller is the one connected\ndirectly to the <glossary>CPU<\/glossary>. One of its DMA channels is used to\nconnect to the slave controller. Because of this, there are actually only seven\nchannels available.\n<\/p>\n<p>\nEveryone who has had a baby knows what an\ninterrupt-driven <glossary>operating system<\/glossary> like Linux goes through\non a regular basis. Just like a baby when it needs its diaper changed, when a\ndevice on the expansion <glossary>bus<\/glossary> needs servicing, it tells the\nsystem by generating an <glossary>interrupt<\/glossary> (the baby cries). For\nexample, when the hard disk has transferred the requested data to or from\nmemory, it signals the <glossary>CPU<\/glossary> by means of an interrupt. When\nkeys are pressed on the keyboard, the keyboard interface also generates an\ninterrupt.\n<\/p>\n<p>\nOn receiving such an <glossary>interrupt<\/glossary>, the\nsystem executes a set of functions commonly referred to as an\n<glossary>Interrupt Service Routine<\/glossary>, or <glossary>ISR<\/glossary>.\nBecause the reaction to a key being pressed on the keyboard is different from\nthe reaction when data is transferred from the hard disk, there needs to be\ndifferent ISRs for each device. Although the behavior of ISRs is different under\n<glossary>DOS<\/glossary> than <glossary>UNIX<\/glossary>, their functionality is\nbasically the same. For details on how this works under Linux, see the chapter\non the <glossary>kernel<\/glossary>.\n<\/p>\n<p>\nOn the <glossary>CPU<\/glossary>,\nthere is a single <glossary>interrupt<\/glossary> request line. This does not\nmean that every device on the system is connected to the CPU via this single\nline, however. Just as a <glossary>DMA<\/glossary> controller handles DMA\nrequests, an interrupt controller handles interrupt requests. This is the Intel\n8259A Programmable Interrupt Controller, or <glossary>PIC<\/glossary>.\n<\/p>\n<concept id=\"\" description=\"The APIC has replaced the 8259A PIC.\" \/>\n<question id=\"\" type=\"TF\" text=\"The APIC has replaced the 8259A PIC.\" \/>\n<p>\nOn newer machines the 8259A PIC has been replaced by the Advanced Programmable Interrupt Controller (APIC) such as the 82489DX or the 82093AA. In fact, Microsoft when so far as to make the APIC a required of the <glossary>PC 2001<\/glossary> design specification. One importance difference between the two is that the APIC allows for a much more complex priority scheme, which is particularly important on system with multiple processes. Originally, <glossary>SMP<\/glossary> capable systems had a proprietary interrupt mechanism. This was then standardized by the implementation of the APIC.\n<\/p>\n<p>\nOn\nthe original IBM PC, there were five “Interrupt Request” lines, numbered 27.\nHere again, the higher the number, the lower the priority. (Interrupts 0 and 1\nare used internally and are not available for expansion cards.)\n<\/p>\n<p>\nThe ISA-Bus also added an additional <glossary>PIC<\/glossary>, which is “cascaded”\noff the first PIC. With this addition, there were now 1615\n<glossary>interrupt<\/glossary> values on the system (2×8-1 because the second is\ncascaded of the first). However, not all of these were available to devices.\nInterrupts 0 and 1 were still used internally, but so were interrupts 8 and 13.\nInterrupt 2 was something special. It, too, was reserved for system use, but\ninstead of being a device of some kind, an <glossary>interrupt<\/glossary> on\nline 2 actually meant that an <glossary>interrupt<\/glossary> was coming from the\nsecond <glossary>PIC<\/glossary>, similar to the way cascading works on the\n<glossary>DMA<\/glossary> controller.\n<\/p>\n<p>\nA question I brought up when I\nfirst started learning about interrupts was “What happens when the system is\nservicing an <glossary>interrupt<\/glossary> and another one comes in?” Two\nmechanism can help in this situation .\n<\/p>\n<p>\nRemember that the 8259 is a\n“programmable” <glossary>interrupt<\/glossary> controller. There is a machine\ninstruction called Clear Interrupt Enable, or CLI. If a program is executing\nwhat is called a <i>critical section <\/i>of code (a section that should not be\nstopped in the middle), the programmer can call the CLI instruction and disable\nacknowledgment of all incoming interrupts. As soon as the critical section is\nfinished and closed, the program should execute a Set Interrupt Enable, or STI,\ninstruction somewhat shortly afterward.\n<\/p>\n<p>\nI say “should” because the\nprogrammer doesn’t have to do this. A CLI instruction could be in the middle of\na program somewhere and if the STI is never called, no more interrupts will be\nserviced. Nothing, aside from common sense, prevents the programmer from doing\nthis. Should the program take too long before it calls the STI, interrupts could\nget lost. This is common on busy systems when characters from the keyboard\n“disappear.”\n<\/p>\n<p>\nThe second mechanism is that the interrupts are priority\nbased. The lower the <glossary>interrupt<\/glossary> request level, or\n<glossary>IRQ<\/glossary>, the higher the priority. This has an interesting side\neffect because the second PIC (or slave) is bridged off the first\n<glossary>PIC<\/glossary> (or master) at IRQ2. The interrupts on the first PIC\nare numbered 07, and on the second <glossary>PIC<\/glossary> the interrupts are\nnumbered 8-15. However, the slave PIC is attached to the master at\n<glossary>interrupt<\/glossary> 2. Therefore, the actual priority is 0, 1, 8-15,\n3-7.\n<\/p>\n<p>\nTable 0-2 contains a list of the standard interrupts.\n<\/p><b>\n<p>\nTable -2 Default Interrupts\n<\/p><\/b>\n<p>\n<table BORDER CELLSPACING=1\nBORDERCOLOR=\"#000000\" CELLPADDING=7 WIDTH=201>\n<tr>\n<td class=\"P10\"><b>IRQ<\/b><\/td><td class=\"P10\"><b>Device<\/b><\/td><\/tr>\n<tr>\n<td class=\"P10\"> 0 <\/td><td class=\"P10\">System timer <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 1 <\/td><td class=\"P10\">Keyboard <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 2 <\/td><td class=\"P10\">Second level <glossary>interrupt<\/glossary> <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 3 <\/td><td class=\"P10\">COM 2 <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 4 <\/td><td class=\"P10\">COM 1 <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 5<\/td><td class=\"P10\">Printer 2 <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 6 <\/td><td class=\"P10\">Floppy <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 7<\/td><td class=\"P10\">Printer 1 <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 8 <\/td><td class=\"P10\">Clock <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 9 <\/td><td class=\"P10\">Not assigned <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 10 <\/td><td class=\"P10\">Not assigned<\/td><\/tr>\n<tr>\n<td class=\"P10\"> 11 <\/td><td class=\"P10\">Not assigned<\/td><\/tr>\n<tr>\n<td class=\"P10\"> 12 <\/td><td class=\"P10\">Not assigned<\/td><\/tr>\n<tr>\n<td class=\"P10\"> 13 <\/td><td class=\"P10\"> Math coprocessor <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 14 <\/td><td class=\"P10\"> Hard Disk <\/td><\/tr>\n<tr>\n<td class=\"P10\"> 15 <\/td><td class=\"P10\">Hard Disk <\/td><\/tr>\n<\/table>\n<p>\nThere’s one thing you should consider when dealing with interrupts.\nOn XT machines, <glossary>IRQ<\/glossary> 2 was a valid\n<glossary>interrupt<\/glossary>. Now on AT machines, IRQ 2 is bridged to the\nsecond <glossary>PIC<\/glossary>. So, to ensure that devices configured to IRQ 2\nwork properly, the IRQ 2 pin on the all the expansion slots are connected to\nthe IRQ 9 input of the second PIC. In addition, all the devices attached to the\nsecond PIC are associated with an IRQ value where they are attached to the PIC,\nand they generate an IRQ 2 on the first PIC.\n<\/p>\n<p>\nThe PICs on an\n<glossary>ISA<\/glossary> machine are <em>edge-triggered<\/em>, which\nmeans that they react only when the <glossary>interrupt<\/glossary>\n<glossary>signal<\/glossary> is making the transition from low to high, that is,\nwhen it is on a transition <i>edge<\/i>. This becomes an issue when you attempt\nto share interrupts, that is, where two devices use the same interrupt.\n<\/p>\n<p>\nAssume you have both a serial port and floppy controller at\n<glossary>interrupt<\/glossary> 6. If the serial port generates an interrupt, the\nsystem will “service” it. If the floppy controller generates an interrupt before\nthe system has finished servicing the interrupt for the serial port, the\ninterrupt from the floppy is lost. There is another way to react to interrupts\ncalled “level triggered,” which I will get to shortly.\n<\/p>\n<p>\nAs I mentioned\nearlier, a primary consideration in the design of the AT Bus (as the changed\nPC-Bus came to be called) was that its maintain compatibility with it\npredecessors. It maintains compatibility with the PC expansion cards but takes\nadvantage of 16-bit technology. To do this, connectors were not changed, only\nadded. Therefore, you could slide cards designed for the 8-bit PC-Bus right into\na 16-bit slot on the ISA-Bus, and no one would know the difference.\n<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Industry Standard Architecture ISA As I mentioned before, most people are generally aware of the relationship between CPU performance and system performance. However, every system is only as strong as its weakest component. Therefore, the expansion bus also sets limits … <a href=\"http:\/\/www.linux-tutorial.info\/?page_id=267\">Continue reading <span class=\"meta-nav\">→<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-267","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"http:\/\/www.linux-tutorial.info\/index.php?rest_route=\/wp\/v2\/pages\/267","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.linux-tutorial.info\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/www.linux-tutorial.info\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/www.linux-tutorial.info\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.linux-tutorial.info\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=267"}],"version-history":[{"count":1,"href":"http:\/\/www.linux-tutorial.info\/index.php?rest_route=\/wp\/v2\/pages\/267\/revisions"}],"predecessor-version":[{"id":580,"href":"http:\/\/www.linux-tutorial.info\/index.php?rest_route=\/wp\/v2\/pages\/267\/revisions\/580"}],"wp:attachment":[{"href":"http:\/\/www.linux-tutorial.info\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=267"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}